The present subject matter relates to semiconductor design technologies; and, more particularly, to a semiconductor memory device having a bit line sense amplifier with small power consumption.
FIG. 1 illustrates an arrangement view of blocks within a conventional semiconductor memory device, which include memory cell arrays, sub holes, bit line sense amplifier block arrays, and word line driving arrays.
As shown in FIG. 1, the conventional semiconductor memory device includes a memory cell array 1 having a plurality of memory cells, bit line sense amplifier block arrays 2 and 3 located at upper and lower sides of the memory cell array 1 for sensing and amplifying data, word line driving arrays 4 and 5 arranged at left and right sides of the memory cell array 1 for selecting the cell memory array, a plurality of S/A controllers 10 for applying an equalization signal BLEQ<0:2>, and a bit line separation signal BISH<0:2> and BISL<0:2> to corresponding sub holes in response to a corresponding cell array selection signal BS<0>, sub holes 6, 7, 8, and 9 for amplifying signals applied from the S/A controllers 10 and applying them to the corresponding bit line sense amplifier block arrays 2 and 3, and a plurality of BLK<0:1> controllers for controlling the driving of the corresponding word line driving arrays 4 and 5 in response to the cell array selection signal BS<0>.
Here, adjacent memory cell arrays share the word line driving arrays and the bit line sense amplifier block arrays with each other. Therefore, it is required to control the operation so that only a selected memory cell array is connected to the bit line sense amplifier block array at the time of data amplification. In this regard, one memory cell and one bit line sense amplifier block will be shown and described in detail.
FIG. 2 is a diagram showing a circuit of a memory cell and a bit line sense amplifier block within a conventional semiconductor memory device.
The circuit shown in FIG. 2 is divided into a memory cell 20 for storing data and a bit line sense amplifier block 30 for sensing and amplifying a voltage level difference of a pair of bit lines to which the data of the memory cell 20 is applied.
More specifically, the bit line sense amplifier block 30 is provided with separation portions 32A and 32B for releasing the connection of the memory cell 20 and a bit line sense amplifier 36 in response to separation signals BISH and BISL, an equalizing portion 34 for precharging and equalizing levels of the pair of bit lines BL and BLB in response to an equalization signal BLEQ, and the bit line sense amplifier 36 which is active by applying voltages to drive power lines RTO and SE, and senses and amplifies a voltage level difference of the pair of bit lines BL and BLB.
For reference, the memory cell 20 is arranged in the memory cell array 1 shown in FIG. 1, and the bit line sense amplifier 36, the equalizer 34 and the separation portions 32A and 32B are arranged in each of the bit line sense amplifier block arrays 2 and 3 shown in FIG. 1.
Meanwhile, as shown in FIG. 2, one memory cell 20 is connected at an upper side of one bit line sense amplifier 36 and another memory cell (not shown) is connected at a lower side thereof. Thus, during a normal operation of amplifying data, the upper and lower separation portions 32A and 32B are provided in order to control the connection of only one of the upper memory cell 20 and the lower memory cell to the bit line sense amplifier 36 according to a selection.
The following is a brief description for driving of the separation portions 32A and 32B. During a precharge interval, since the upper and lower separation signals BISH and BISL all have a logic high level, it can be seen that the separation portions 32A and 32B become active and thus, the upper memory cell 20 and the lower memory cell are all connected to the bit line sense amplifier 36 through the pair of bit lines BL and BLB. If the upper memory cell 20 is selected, the upper separation signal BISH has a logic high level and the lower separation signal BISL has a logic low level. Therefore, it can be seen that the upper memory cell 20 is still connected to the pair of bit lines BL and BLB by the upper separation portion 32A, but the lower memory cell is disconnected from the pair of bit lines BL and BLB by the lower separation portion 32B.
Meanwhile, as mentioned above, the upper and lower separation signals BISH and BISL that control the driving of the separations portions 32A and 32B are supplied from the S/A controller 10. The following is a detailed description of the conventional art that controls the activation of the separation signals BISH and BISL during the driving of the S/A controller 10.
For reference, the upper separation signal BISH is a signal for controlling the connection of the memory cell 20 arranged at the upper side of the bit line sense amplifier block 30, and the lower separation signal BISL is a signal for controlling the connection of the memory cell (not shown) arranged at the lower side of the bit line sense amplifier block 30.
FIG. 3 is an internal circuit diagram of the S/A controller 10 for controlling the switching of a pair of bit lines BL and BLB within the conventional semiconductor memory device.
Referring to FIG. 3, the conventional semiconductor memory device includes a delay circuit 12 for delaying and inverting a cell array selection signal BS<0>, and a level converter 14 for inverting an output signal of the delay circuit 12 to output an upper pre-separation signal BISHLB of high voltage VPP level.
For reference, an upper separation signal BISH that controls the switching between the bit line sense amplifier and the bit lines has an inverted logic level of the upper pre-separation signal BISHLB.
Hereinafter, the operation of the S/A controller 10 within the semiconductor memory device shown in FIG. 3 will be described.
First, a normal operation when a memory cell array is selected will be discussed. When an active command ACT and a row address are applied from outside, the cell array selection signal BS<0> is activated to a logic high level for rendering the corresponding memory cell array active. Then, the delay circuit 12 inverts the cell array selection signal BS<0> to provide an output signal of logic low level. In succession, the level converter 14 outputs the upper pre-separation signal BISHLB of logic high level in response to the output signal of logic low level from the delay circuit 12.
Thus, the upper memory cell 20 is connected to the bit line sense amplifier block 30 through the pair of bit lines BL and BLB in response to the upper separation signal BISH which is activated to the logic high level.
For reference, the control block for generating the lower separation signal BISL has the same circuit implementation as that of FIG. 3, except that it receives BS<1> as the cell array selection signal. Therefore, a further description thereof will be omitted here for simplicity.
Next, a normal operation when a memory cell array is not selected and a case in which a precharge command is applied will be discussed.
When the memory cell array is not selected, the cell array selection signal BS<0> has a logic low level. Then, the delay circuit 12 outputs the activation sense signal of logic high level in response to the deactivation of the cell array selection signal BS<0>. Subsequently, the level converter 14 outputs the upper pre-separation signal BISHLB of logic low level.
Further, when a precharge command PCG is inputted, the selected cell array selection signal BS<0> is deactivated and thus, the same operation is carried out, as in the case where the memory cell array is not selected.
Therefore, when the upper separation signal BISH is deactivated to a logic low level, the connection between the upper memory cell array 20 and the bit line sense amplifier block 30 is disabled.
Further, the cell array selection signal BS<0> is a signal that is activated to select the corresponding memory cell array in response to the active command ACT and the row address being applied therewith.
As mentioned above, since the conventional semiconductor memory device receives the cell array selection signal BS<0> that is generated by the active command ACT and the row address being applied thereto and deactivated by the precharge command PCG, and generates the upper separation signal BISH, the upper separation signal BISH is toggled whenever the active command ACT and the precharge command PCG are applied. In other words, during the normal operation, the conventional semiconductor memory device repeatedly performs the process in which the memory cell array and the pair of bit lines are connected by the active command ACT and the row address and then the switching is made in response to the precharge command PCG being applied.
In this manner, the separation signal is switched from a logic high level to a logic low level, and vice versa, whenever the active command ACT and the precharge command PCG are applied, so that current consumption occurs by such toggling.
Further, the separation signal has a high voltage level that is created by charge-pumping a core voltage within the device, and thus, current consumption by toggling is very large. Moreover, since the efficiency of high voltage generation is about 25% to about 30%, current consumption caused by such toggling in the entire device may be about three to about four times that of a switching current of the separation signal.